1. Field of the Invention
The invention relates to the field of redundant circuits, particularly for use in single chip memories.
2. Prior Art
It is well known to use redundant memory circuits on a systems level to increase reliability, and on a chip-level to improve production yields. See U.S. Pat. Nos. 4,047,163; 4,250,507 and "Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement", IBM J. Res. Develop. Volume 24 No. 3, May 1980 by Fitzgerald and Thoma for discussions concerning chip level redundancy.
In some memories with redundant cells, faulty cells are first identified during probe testing of the wafer and then fuses are blown to allow selection of the redundant cells. In some cases, particularly on dynamic RAMs and EPROMs, it is preferable to select redundant cells after the chip has been packaged since faulty cells are often first detected after the chip has been packaged. As will be seen, the present invention provides a redundancy apparatus which permits selection of redundant cells after the chip has been packaged. Importantly, no extra package pins are required for the programming operation used to permanently select the redundant cells which replace the defective cells.
One problem area which arises where redundancy programming is possible at the package level, is that the user may inadvertently reprogram the redundancy circuits. Such inadvertent programming could cause a user, for example, to permanently select a faulty redundant line, or cause other problems. The present invention provides a mechanism for permanently disabling the programming circuitry, thus preventing a user from inadvertently programming or reprogramming.